KAN1101 Wideband Analog Front End IC
KAN1101 is among MCC’s high-end integrated analog front end (AFE series) family of products. KAN1101 provides high performance, low power, and cost effective solution for home networking applications, wireless base station, and so on. KAN1101 integrates two analog-to-digital converters (ADC), programmable gain amplifier (PGA), analog channel equalizer (ACE), one digital-to-analog converters (DAC), one current amplifiers (IAMP), one clock synthesizer (LC-based), one 3.312Gbps serializer/deserializer (SerDes), serial peripheral interface (SPI), and digital signal processing units (DSP). KAN1101 is available in 65nm CMOS technology.
The figure below shows the AFE overall block diagram. PGA has the function of ACE to compensate higher frequency signals which are largely attenuated over long distance which usually results in lower SNR on receiver side. DAC is 12-bit 424Msps. Two ADCs are identical and operating at 12-bit 212Msps to achieve 12-bit 424 Msps by means of time interleaved manner. The 12-bit sampling data is transferred between the baseband (Digital PHY) chip and KAN1101 via the SerDes at 3.312Gbps serial bit stream. A simple protocol to convert the 12-bit to the serial bit stream and vice versa is defined as the ASI (AFE Serial Interface), which is compatible with JESD 204A (JEDEC standard, serial interface for converters). The ASI defines framing, scrambling, 8B/10B coding, establishing and maintaining the 3.312Gbps link. The serial interface, as adopted by many similar standards provides a number of advantages which include simpler PCB design, reduced EMI, lower pin counts, etc. Tx can provide a full scale current in the range of 4mA to 200mA by IAMP. IAMP can be bypassed. Note that either IAMP enabled or bypassed can be chosen at a time (these are exclusive). The PGA gain can be configured from -18 dB to 24 dB. The clock synthesizer is an LC-VCO based PLL technology with low jitter employing the 35.328MHz Xtal input as its reference clock. The sampling clocks and the differential reference clock to the SerDes are derived from the PLLs and are carefully routed to maintain the signal quality and integrity. The differential reference clock is also output on IFCKOP/N through LVDS driver. The frequency of the differential clock is 132.48MHz. It shall be used as the reference clock of the SerDes in a baseband chip for ASI.
The digital signal processing units realize FIR filters, such as pre-emphasis, interpolator, decimator, and calibrations for DAC, PGA, and ADCs. The DSP units are among the important blocks within KAN1101 to maintain the utmost performance. KAN1101 provides the optimum control for power consumption within the device by switching on/off each component’s operation. The target system can be optimized by configuring KAN1101 via the three or four wire SPI Interface.
- 65nm CMOS Wide Band AFE IC
- 12mm x 12mm VQFN 88-pin 0.5mm pitch, or, 10mm x 10mm VQFN 88-pin 0.4mm
- High speed sampling rate and low power
- High resolution and wide frequency range
- Deep Sleep Mode Operation
- Up to 212 Msps data rate
- 12-bit 424Msps DAC
- Pre-emphasis filter
- Selectable low pass ( 0-95.4MHz or 0-100MHz ) and high pass ( 116.6MHz-212MHz or 112-212MHz ) mode 2x interpolator
- Integrated 200mA line driver with 20dB gain control (bypass mode is supported)
- 12-bit 424Msps by means of 2x 12-bit 212 Msps ADC with time interleaved manner
- Low-noise PGA with ACE
- Selectable low pass ( 0-95.4MHz or 0-100MHz ) and high pass ( 116.6MHz-212MHz or 112-212MHz ) mode /2 decimator
- Integrated low-jitter clock synthesizer (PLL)
- 3.312Gbps high speed serial interface as the digital interface (compatible with JESD204A)
- IFCKOP/N are the clean 132.48MHz clock output to be used as the reference clock for a baseband chip
- Integrated fine and accurate foreground calibration on TxDAC and RxADC path