Process Technology  

MegaChips is a pioneer in the ASIC industry in using foundries.  In 1997 we adopted a fabless business model for advanced process technologies. The fabless ASIC supplier model is being adopted by many of our competitors today – we have a decade of experience with it!  The benefit to customers of this 10-years of experience include on-time delivery through a smooth supply chain and affordable prices through strong relationships with our fab partners.

MegaChips works with and sources from multiple foundries such as TSMC, UMC, GlobalFoundries, Samsung, and STMicro to achieve the ultimate combination of low power, high performance, high yield and exceptional reliability at the lowest cost.

MegaChips Process Technologies

Product
Family
Geometry (Drawn) Core Voltage (V) I/O Voltage (V) Max.
Metal Layers
Gate
Density (Kgates/
mm2)
Fab
Standard Cell
K28HPC 28nm 0.9 HPC 2.5/1.8 10 4500 Multiple
K40G K40L 40nm 0.9 GP 1.1 LP 3.3/2.5/1.8 10 1620 Multiple
K65G K65L 65nm 1.0 GP 1.2 LP 3.3/2.5/1.8 9 854 TSMC
KS8500 90nm 1.0* 3.3/2.5 9 457 TSMC
KS7500 0.13μm 1.2 3.3/2.5 8 256 TSMC
KS6500 0.15μm 1.5 3.3 7 180 UMC
KS6000 0.18μm 1.8 3.3 6 94 UMC &
He Jian

* Supports Voltage Islands

High Density Libraries

Process technology is just one part of the story – libraries are the other part.  MegaChips’s 7-grid libraries provide higher gate densities than those of competitors:

ASIC Supplier 0.13µm Standard Cell Library Density (Kgates/mm2) Source
MegaChips 256 MegaChips
IBM 175  (MegaChips is 46% denser) Source Link
ST 200  (MegaChips is 28% denser) Source Link

Virage Logic is the source for MegaChips’s 7-grid libraries.  MegaChips helped Virage develop their 7-grid ASAP Logic Ultra-High Density (UHD) libraries.  By compacting cells into a 7-high grid, MegaChips libraries are able to achieve higher gate densities than 8-grid (or higher) libraries used by competitors.  The benefit to customers of our higher density libraries is lower unit costs.

MegaChips “Rainbow Wafer”

Another important differentiation between MegaChips and some other fabless ASIC suppliers is the process we follow to validate the design of physical IP (such as SerDes, PLLs, etc.) before allowing it to be used by our customers.  MegaChips uses “Rainbow Wafers” to ensure that any physical IP in our IP portfolio will work over the entire valid process spectrum:


Figure 1: MegaChips Rainbow Wafer