MegaChips’s ASIC testing methodology includes full scan insertion, memory BIST insertion, and Iddq testing. In addition to performing final high-speed testing, MegaChips also supports JTAG boundary scan register (BSR) insertion. Our state-of-the-art test center has dozens of test machines – including state-of-the-art Advantest and HP testers.
To help identify manufacturing defects, MegaChips is able to insert scan chains into the ASIC as a service to our customers. To minimize the effects of scan insertion on performance, we provide customers with pre-scan libraries that incorporate the effects of scan insertion on performance and die area. MegaChips also uses proprietary tools to prevent scan chain shift errors. We create vectors from the scan chain, which we use to test the ASIC before shipment to customers. MegaChips’s scan insertion techniques ensure very high fault coverage.
MegaChips uses BIST to test its memories for manufacturing defects. Our controller adds minimal overhead (about 1,000 gates) and a single controller supports dozens of memory blocks. Multiple controllers can be instantiated into hierarchical designs.
MegaChips uses advanced Iddq testing to help identify manufacturing defects in its ASICs. We use automatic address selection techniques to measure thousands of addresses. We also utilize fast DC measurement techniques to conduct Iddq testing in a quick and cost effective manner.
JTAG (IEEE 1149.1 compatible)
MegaChips’s JTAG support includes providing customers with the Test Access Port Controller, and BSDL files.